This patent application claims the benefit of Japanese Patent Application No. 2016-157428, filed on Aug. 10, 2016. The content of the aforementioned application is incorporated herein by reference in its entirety.
1. Technical Field
The present invention relates to a semiconductor device incorporating an electrically rewritable non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash memory, and a production method thereof.
2. Related Art
It is known that there are two types of electrically rewritable non-volatile memories: a floating gate type memory; and a charge trap type memory. The floating gate type memory is configured such that a floating gate electrode is provided between two gate insulating films of a memory transistor, electric charges are accumulated in the floating gate electrode, and data is thereby stored.
On the other hand, the charge trap type memory is configured such that a gate insulating film of a memory transistor has a stack structure (ONO structure) including a silicon oxide film, a silicon nitride film and a silicon oxide film, and electric charges are accumulated in discrete traps that are present in the silicon nitride film near the interface between the silicon nitride film and the silicon oxide film (tunnel film) that is provided on the silicon substrate side. The threshold voltage of the memory transistor thereby changes, and thus data can be stored. Such a memory transistor is also called MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Semiconductor).
In the case of the charge trap type memory, because electric charges are accumulated in the silicon nitride film that is an insulating film, even if the insulation property of the tunnel film drops to a level slightly lower than that of the floating gate type memory, it does not become a problem. Also, the thickness of the tunnel film can be reduced, and thus a data write voltage can be lowered. However, there is a problem in that if the production process for producing a semiconductor device ends with the electric charges accumulated during the production process being trapped in the silicon nitride film, the threshold voltage varies as compared to a state in which electric charges are not trapped in the silicon nitride film.
As a related art, JP-A-2013-179122 (paragraphs [0013] to [0014] and [0037] to [0040], and FIG. 2, hereinafter referred to as Patent Document 1) discloses a non-volatile semiconductor memory that solves the above-described problem. A non-volatile semiconductor memory 200 disclosed in FIG. 2 of Patent Document 1 includes a silicon substrate 12, a first silicon oxide film 20 stacked on the silicon substrate 12, a first silicon nitride film 21 stacked on the first silicon oxide film 20, a second silicon oxide film 22 stacked on the first silicon nitride film 21, a third silicon oxide film 30 that is provided on the silicon substrate 12 and is adjacent to the first silicon oxide film 20, and a second silicon nitride film 23 having a first portion that is in contact with the first silicon nitride film 21 and a second portion that is in contact with the silicon substrate 12 via the third silicon oxide film 30.
With this configuration, the second silicon nitride film 23 is in contact with the first silicon nitride film 21 and is also in contact with the silicon substrate 12 via the third silicon oxide film 30, and thus excess electric charges (process charging) trapped in the first silicon nitride film 21 during the production process can be diffused into the silicon substrate 12 via the second silicon nitride film 23 and the third silicon oxide film 30 in another production process. Accordingly, it is possible to reduce the influence of process charging on the threshold voltage of the memory transistor and achieve an increase in the speed and a reduction in voltage of the memory.
The memory transistor included in the non-volatile semiconductor memory 200 shown in FIG. 2 of Patent Document 1 has, even in a side wall portion, an ONO structure in which the third silicon oxide film 30, the second silicon nitride film 23, and a silicon oxide film 11 are stacked. In the case where such a memory transistor is formed on the same semiconductor substrate together with a MOS transistor in a peripheral circuit, if these transistors are produced in the same process, a similar ONO structure is formed on the side walls of the MOS transistor, and the ONO structure functions as a parasitic memory cell.
For example, in the case where an N channel MOS transistor is formed in a P well, if a reference potential is applied to the gate of the MOS transistor and also a high potential is applied to the drain of the MOS transistor, hot carriers (holes) are generated and pulled by a gate potential and trapped in the silicon nitride film of the parasitic memory cell. As a result, electrons are attracted to a region in the semiconductor substrate immediately below the parasitic memory cell, and the state is equivalent to a state in which the N-type impurity concentration is partially high, which increases a leak current in the PN junction and causes the characteristics of the MOS transistor to vary.